This invention generally relates to simulators in switched power electronic circuits and more particularly to a method and system for reducing spurious power losses and signal overshoots in real-time/non real-time simulators for switched power electronic circuits.
A real-time simulator is a device that emulates the real-time behaviour of a system or apparatus at real-life speed. Real-time simulators comprise elements that are typically based on computers or similar digital computing devices that compute the apparatus-governing-equations, which typically include a set of Differential-Algebraic Equations (DAEs). Practically, the system/apparatus may comprise ‘controlled devices’, meaning that they normally work in conjunction with a controller. The controller has the objective of effectively controlling the apparatus within certain objectives and requirements. In real life, the performance of the device (also known as the ‘plant’) is controlled by accepting the commands of the controller. The controller adjusts its commands by reading the device parameters/states (e.g., currents, position, speed). Expediently, the controller and controlled devices are connected in a closed-loop. The study of the behaviour of a controlled device and a controller connected in a closed-loop is a complex subject. Although basic PID (Proportional Integral Derivative) control can be studied using analytical methods, non-linear behaviour, fault modes and protection considerations add to the complexity so much that it becomes significantly difficult to validate a controller analytically.
By using a real-time simulator, engineers can test and validate the control laws of the controller in a safe environment, without risk of injuries, by replacing the real apparatus by a virtual one (especially in high power applications such as ships, planes, electric plants or grids). Simulators are often used also in cases where it is not even possible to use a real plant, for example to test protection limits in borderline conditions.
The real-time simulator itself generally comprises two main parts: a computing unit (—CPU, FPGA, GPU, or a combination of these—), running-models of a simulated apparatus and an input/output (I/O) interface. These I/Os connect the simulated controlled device to the controller under test. These I/Os are typically sets of analog inputs and outputs, and digital inputs and outputs. For example, the digital input will read the controller pulse that drives a switching converter (—power electronic converter—) simulated in the real-time simulator. Current and voltage values of the switching converter will be sent to the analog output of the simulator so that these values can be read by the controller. I/Os are required to close the loop between the real controller in the real world and the emulated controlled device. To synchronize the real-time simulator at real world time, the real-time simulator includes an internal clock, which can come from an I/O device or be generated by the operating system. It is also noted that the computing unit must be fast enough and/or use fast-enough algorithms to be able to compute and iterate the model states and outputs at the real-time pace. This is necessary to enable interaction with a real device connected to the I/O of the simulator.
Real-time simulation technologies are nowadays an integral part of the design and test process of many types of electric systems like large power grids, power converters and variable speed drives. These modern design approaches mitigate the risks through extensive use of technologies like Hardware-In-the-Loop (HIL) simulation and the model-based design approach. In HIL simulation, a plant controller is tested against a real-time simulated model of the plant. HIL simulation technologies enable more gradual integration, while diminishing the risk and costs of such projects. Also, in HIL simulation, more elaborate test coverage can be achieved than is possible using analog prototypes because of the safe operational limits of real power electronic devices and power plants.
Non real-time applications of real-time simulator.
FIG. 1, explained in more detail later, shows the real-time simulator usage in HIL with a controller under test. A real-time simulator can also be used without externally-connected controllers. This is the case in tests involving batch testing, and what is known as Monte-Carlo testing, with a large number of statistically varying test-cases. Note that Monte-Carlo tests can also be made in HIL mode. For example, this approach is used by utilities to correctly assess the protection of a power system. In this case, the same real-time solvers can be used, and the internal clock can be adjusted to suit the actual computation-time of the solver. Such usage of the simulator is sometimes viewed as being faster-than-real-time because in small power electronic systems it can result in simulation that is faster than in real-time. All applications of real-time simulators are therefore generally applicable to non-real-time simulators as well.
Human-in-the-Loop simulation
Real-time simulators are also often used to train operators with real-time simulated devices computed on the real-time simulator. This is generically similar to the configuration in FIG. 1 except that the ‘controller’ is a human person with I/Os adapted for human perception and actions. These I/Os may in this case be a graphical display, a keyboard, or a joystick, or the like.
Real-time simulation of switched power electronic systems
Real-time simulation of power converters is however very challenging for several reasons. The source of the challenge lies in the mandatory use of fixed-step solvers in a real-time simulator. Typical power converters are composed of a large number of switching devices operating at commutation frequencies that can be very high with regard to the sampling time of the real-time simulator. For example, it is not uncommon presently to commission power grid devices called FACTS devices with several hundred switches. These switches then create a large number of electrical modes that are difficult to compute using the class of real-time solvers. Second, the sampling time of the real-time simulator may be insufficient to correctly sample the PWM waveforms that often drive these converters. Additionally, many power converter configurations create instantaneous switching events that are hard to handle with non-iterative solvers. A good example of a converter that induces instantaneous events is the boost converter, wherein when the IGBT (Insulated Gate Bipolar Transistor) opens, the diode turns on immediately.
Finally, it is important to understand that these challenges are partly caused by speed limitations of the computational hardware available presently. In that regard, two main classes of hardware are used presently to design real-time simulation of power converter circuits: CPUs (as part of a computer system) and FPGAs. Each class of hardware has pros and cons. The structure of CPUs as well as derivative similar devices such as ARM (Advanced RISC Machines) allows them to implement complex algorithms and solvers. Also, the use of high-level languages like ‘C’ for example, facilitates their implementation. However, the costs of conversion to machine-code (i.e. compilation), as well operating system and I/O bus latencies limit this approach to sample-times above 2-5 μs. On the other hand, this sample-time can go down to 5-10 nanoseconds in FPGAs (˜1000 times lower than the sample-time in CPUs) but their internal structure limits the use of complex solvers and favors simpler ones.
For power systems and power electronic simulation and real-time simulation, the most common DAE (differential-algebraic equation) solver is the so-called ‘Nodal Admittance Method’ (NAM), sometimes referred to as the Dommel method. In NAM, the dynamic equations of elements such as resistances, inductances, capacitors, and other non-linear elements are made discrete with the trapezoidal rule of integration, which is an implicit integration method. The implicit integration method used creates discrete equations that cannot be iterated on their own as the current at time t, i[t], depends on the voltage at time t, v[t]. This problem is solved by combining all elements into a set of equations using the method of NAM. It is noted that the ratio of i[t]/v[t] is an admittance factor, and all elements must conform to the algebraic constraint (i.e. Kirchhoff voltage and current laws) created by their connections.
In NAM, switches are modeled as binary resistive switches: ‘ON’ if a switch is conducting, (it is modeled as a very small resistance or null resistance in some implementations) and ‘OFF’ if the switch is not conducting (it is modeled as a very high resistance or infinite resistance in some implementations) One of the main difficulties of implementing the NAM solver in real-time with these binary switches is that it requires a matrix re-factorization. Matrix re-factorization is a relatively computationally intensive operation that often limits the speed and size of real-time simulation in modern simulators. This re-factorization/inversion must be done each time the switching device toggles on and off in a simulation. Inversion must also be done if other non-linear devices change the operating point. NAM has variations like Augmented Nodal Admittance method and Modified Augmented Nodal Admittance (MANA) method. The original NAM however is most common in modern real-time simulators. The above NAM method originates from the well-known Kirchhoff electric circuit laws. The Kirchhoff current law states that the sum of currents entering a node must be zero. Similar laws exist in other domains. Hydraulic flows obey similar laws in pipe systems, and in aircraft hydraulic system simulation for example, the sum of flows at a given node must equal zero. This is to say that the nodal admittance method and the invention use principles that can be derived from other fields of engineering but they are mathematically analogous.
NAM solver without re-factorization: Pejovic solver
In what is known as a Pejovic solver, the NAM solver portion is modified to avoid re-factorization. The method models switching devices not as a binary switch as in conventional NAM, but as either a small capacitor when OFF and a small inductor when ON. If the following constraint is observedgs=C/h=h/L  (1)with C being the capacitance in Farads used when the switch is OFF or non-conducting, L being the inductance in Henrys used when the switch is ON or conducting and ‘h’ being the simulation-time-step in seconds, then re-factorization is not required and the simulation speed is increased, which is especially advantageous for real-time simulators. The ratio C/h=h/L is also called the Pejovic conductance gs. This C/h=h/L ratio is valid for backward Euler discretization, and other discretization methods result in similar equality constraints. For example, discretization with the trapezoidal method results in the (2*C)/h=h/(2*L) equality constraint. This method is often called Fixed Admittance Matrix Nodal Method (FAMNM). The FAMN-Method is used in many real-time simulators like the Maguire simulator. However, FAMNM suffers from two well-identified problems:    1—The use of L/C components for switches notably induces spurious losses in the simulation.This can be explained as follows: each time a capacitor or inductor disappears from the simulation, the energy contained in it also disappears. An inductor L with a current i in it contains an energy equal to E=½Li2. A capacitor C with a voltage v across it contains an energy equal to E=½Cv2. When the switching frequency increases, these spurious losses can become excessive. In this case, a simulated controlled device will exhibit higher power losses than its real life counterpart, and the real-time simulator becomes inaccurate.    2—The use of L/C components for switches induces spurious overvoltages and over-currents in the simulation.This can be explained because when L-C components interact together in a circuit, oscillatory modes are created. The L/C components of the Pejovic method are known to add some oscillations at switching instants, much like when one energizes an L-C resonant circuit.
In an approach and method taught by Hui, the FAMN method is derived from the usage of so-called ‘stublines’ but the obtained method is basically the same as the Pejovic method resulting in a fixed nodal admittance method and with capacitive or inductive switches. The discrete equations of the switches in Hui are generally the same as in Pejovic, but only derived differently; therefore the present invention applies to both. Hui is cited as the basis of the RTDS FAMNM in Maguire wherein, the technique is clearly described as a fixed admittance matrix and with switches being an inductor or a capacitor.
Many of the prior art methods including methods taught in Maguire, Dufour and Razzaghi recognize the problem of over-voltage/current and/or power losses, and propose various methods to minimize the effects. Many other prior art methods focus on the optimization of the inaccuracies of the method and the decrease of the losses by choosing the best conductance value or gs value (gs=h/L=C/h). In Maguire specifically, the method tries to minimize overvoltage/over currents by using an RC circuit instead of C in the OFF state of the switch. Therein, the combined RC and L are adjusted to damp overvoltage/overcurrents only, but without affecting the power losses. In the Maguire paper, the OFF state of the switch is chosen to be an R-C circuit instead of a pure capacitor with the objective of reducing the Pejovic overvoltages/overcurrents, but the Maguire paper clearly mentions that the Pejovic Capacitor and Inductor energies are lost because of the use of FAMNM.
No prior art approach thus far has taught or used the method and apparatus of the present invention.
In some circumstances, the addition of a resistance to the OFF-state of the Pejovic switch can actually increase the losses. This can be explained considering that, to maintain a constant gs, one must increase the capacitor C to compensate for the increase in R (i.e. 1/gs=R+b/C). The increased capacitor value may just cause more losses because the maximum stored energy ½CV2 is greater than without R. The same remark goes for a possible but rarely used variation of the Pejovic method when the L ‘ON’ equivalent is replaced with an inductance and resistance in parallel.
Nevertheless, the present invention is also applicable to the foregoing R-C variation of the Pejovic method described in the arrangement taught in the Maguire method. In the Pejovic method, the choice of gs affects the accuracy of simulation because it changes the values of inductance and capacitance that are inserted and removed each time a switch turns ON or OFF. Much work has been done in the past to try to find an optimal value of this Pejovic conductance as in what is known as the Razzaghi method and also the Maguire type simulator with the RC model for the OFF state switch.
Calculation of FAMNM induced losses in a 3-phase 2-level inverter:
The FAMNM losses can be computed analytically from a simple inverter case. Take for example a 3-phase two-level inverter connected to a 3-phase load, as depicted in FIG. 1. Derived hereinafter is a formula to compute the switch losses in a typical FAMN Method for a 3-phase inverter outputting three-phase currents into a load from an ideal DC source, as illustrated in FIG. 2. that uses six controlled switches(—as explained later—).The cause of the losses of the FAMN Method is that each time a switch changes state, it loses the energy associated with its L/C model. In the inverter, it is noted that:                Just before a switch is turned ON, it had the DC-link voltage applied to its terminals.        Each switch carries the load current before it is turned OFF.        Each switch is turned on and off fpwm times per second.The following are defined:            fpwm: PWM frequency of the drive    fload: Frequency of the currents    Ieff: Load current (RMS value)    Vdc: DC voltage being invertedConsidering that the 6 switches all have the same voltage V before they are turned on, the turn-on loss is then:Pon=6*0.5*C*Vdc2*fpwm Watts  (2)The switches also cut off the load current which has a fload frequency. Consider hypothetically that the PWM frequency is an exact multiple of the load frequency K=fpwm/fload The turn off power is then:
                              P          off                =                  6          *          0.5          *          L          *                      f            pwm                    ⁢                                    ∑                              k                =                0                                            K                -                1                                      ⁢                                          2                            ⁢                              I                eff                            ⁢                                                cos                  2                                ⁡                                  (                                      2                    ⁢                    π                    ⁢                                                                                  ⁢                                          k                      /                      K                                                        )                                                                                        (        3        )            which can be reduced toEoff=6*0.5*L*fpwm*Ieff2  (4)The total loss is then equal to:Ptot=3*fpwm*{C*Vdc2+L*Ieff2}  (5a)orPtot=3*fpwm*h*{g*Vdc2+1/g*Ieff2}  (5b)with h being the time step and gs being the {L,C} discrete admittance value of the FAMNM switch using the Backward Euler method. A similar formula can be obtained for the Trapezoidal Rule of integration.
From Eq. 5a, it is seen that a minimum loss can be realized by choosing gs correctly. A similar observation is also made in Maguire in the Maguire-publication. It is noted in this context that the problem of FAMNM losses is well-known in literature.
The losses discussed supra are induced by the FAMN Method and are eliminated or reduced by the present invention.